The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to the in-line monitoring of an on-going CMP process using scatterometry to optimize and to determine an endpoint for the on-going CMP process.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and size of memory cells, and surface geometry of various features such as corners and edges.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The photoresist receives a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the photoresist. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the photoresist through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the photoresist as less soluble polymer. are removed in the developing process to leave the pattern image in the photoresist as less soluble polymer.
The patterned photoresist is subsequently employed to replicate its pattern image onto one or more layers formed on the wafer. Layers of photoresist, conductive, polymeric and insulative materials are routinely applied to wafers multiple times during a manufacturing process for integrated circuits, as one of a sequence of steps to produce a desired lithographic pattern. Thickness and uniformity of the layers is critical to the overall functionality of the manufactured device. The goal of the photoresist application process as well as subsequent layering processes is to achieve uniform layers on the wafer surface. This goal can be achieved by planarizing the layers in order to obtain a desired thickness and uniformity.
One technique that is used in the semiconductor industry for planarizing layers is chemical mechanical polishing (CMP). Chemical mechanical polishing involves holding and rotating a semiconductor wafer against a wetted polishing platen under controlled chemical, pressure and temperature conditions. Typically a slurry solution is used as the abrasive fluid. The polishing mechanism is a combination of mechanical action and the chemical reaction of the material being polished with the slurry solution. As circuit densities increase, chemical mechanical polishing has become one of the most viable techniques for planarization. However, CMP is not without its share of difficulties.
Conventional CMP processes check planarization parameters near or at the end of polishing or at pre-scheduled intervals of time. These types of post-polishing and interval detection methods can be problematic for several reasons. For example, pre-scheduled interval endpoint detection methods are generally based on past wafer characteristics. Thus, they may not account for structural and layer variations which may exist among wafers. As a result, over, under, or uneven polishing may occur despite the interval endpoint detection method employed. Although some poorly polished wafers may be reparable, repair costs and associated manufacture delays may be too burdensome and less cost-effective than discarding them. Furthermore, poor polishing may cause irreparable damage, forcing the damaged wafers to be discarded.
In addition, post-CMP detection methods do not provide a user with real-time information relating to the polishing (smoothing) of the wafer, thereby making it difficult to determine when to terminate a given CMP process before an appropriate endpoint has passed. Furthermore, post-CMP data limits the user to large-scale estimations for determining an appropriate CMP endpoint, resulting in recurring polishing errors, which contribute to yield loss, increased manufacturing costs and decreased performance in the semiconductor devices. In light of these problems, there is an unmet need for monitoring the CMP process in order to determine an appropriate endpoint for terminating the polishing process. In addition, there is an unmet need for optimizing an on-going CMP process.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides an in-line system and an in-line method for monitoring a CMP process with respect to a layer or wafer undergoing planarization and/or smoothing. More specifically, the present invention provides an in-line system and an in-line method for determining a termination point for an on-going CMP process and for optimizing the on-going CMP process to affect current and future wafers. This is accomplished in part by conducting the CMP process with scatterometry feedback corresponding to a thickness and a profile of the wafer.
One aspect of the present invention relates to an in-line system for monitoring a CMP process containing a wafer, wherein the wafer is subjected to the CMP process; a CMP device comprising one or more CMP components, wherein the CMP device performs the CMP process; a CMP process monitoring system for generating a signature associated with wafer dimensions undergoing a CMP process step; a signature library to which the generated signature is compared to determine a state of the wafer; and a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer structure.
Another aspect of the present invention relates to an in-line system for measuring thickness and profile of a wafer undergoing a CMP process containing a CMP device comprising one or more CMP components, wherein the CMP device performs the CMP process; a light source for directing light at a wafer, wherein the wafer is subjected to the CMP process; a light detector for collecting the light reflected from the wafer; a signature library comprising signatures associated with known wafers which have been subjected to the CMP process; a CMP analysis system, operatively coupled to the light detector and the signature library for generating a signature corresponding to the reflected light to determine dimensions of the wafer undergoing the CMP process; and a closed-loop feedback control system for optimizing the CMP process according to the determined wafer dimensions to make one or more changes to the CMP device.
Yet another aspect of the present invention relates to using scatterometry in an in-line system for determining an endpoint of a CMP process. The system contains a CMP device comprising one or more CMP components, wherein the CMP device performs the CMP process; a light source for directing light at a wafer, wherein the wafer is subjected to the CMP process; a light detector for collecting the light reflected from the wafer; a signature library comprising signatures associated with known wafers which have been subjected to the CMP process; a CMP analysis system, operatively coupled to the light detector and the signature library for generating a signature associated with the reflected light to determine dimensions of the wafer undergoing the CMP process; a CMP controller operatively coupled to the CMP monitoring system and a CMP driving system for determining the endpoint of the CMP process, wherein the CMP controller operatively controls the CMP process via the CMP driving system using closed-loop feedback control; and a trained neural network operatively connected to the CMP controller to facilitate optimization of the CMP process.
Still yet another aspect of the present invention relates to an in-line method for monitoring a CMP process by generating a signature corresponding to a wafer undergoing a CMP process. The method involves the steps of providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer structure.
Still another aspect of the present invention relates to using scatterometry in an in-line, closed-loop method for determining an endpoint to a CMP process. The method involves the steps of providing a wafer, wherein the wafer is subjected to a CMP process; directing a beam of incident light at the wafer; collecting light reflected from the wafer; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine dimensions of the wafer; determining whether the wafer dimensions are within a pre-determined acceptable range; if the wafer structure dimensions are within the acceptable range of values, then instructing a CMP driving system via a controller to terminate the CMP process; and if the wafer structure dimensions are not within the acceptable range of values, then instructing the CMP driving system via a controller to adjust one or more CMP process components and to continue the CM P process for the wafer structure.